The ICISS1/CDi3 used the DIP version of the Zilog Z8S180, the CPU, it was limited to a maximum clock rate of 10MHz. There was a 20MHz maximum DIP version manufactured some time ago, we only managed to buy one but that's now irrelevant because all DIP packages are obsolete. Top family clock rate is 33MHz and one can buy 33MHz chips in the marketplace, but only in QFP and/or PLCC packages.

The QFP package (local picture) is a Surface-Mounted Device, SMD, so it must be soldered directly to the PCB traces, the PLCC package (local picture) of the chip is also an SMD but this one can optionally be socketed in which case we are likely to have a problem because the socket's height is over 1/4" and this might make it difficult to fit the flipped memory board right over it. We will most likely select the QFP version, the whole assembly is moving from through-hole to SMT.

The 2000 ICISS had a 6.144MHz crystal in it but its clock rate was only half of that due to a programmable divide by two flip-flop inside the chip. The recent modifications and upgrades brought about the usage of a 7.3MHz crystal and this resulted in a unit with both low and high speeds, namely, 7.3MHz or 3.65MHz. The 7.3MHz mode results in a maximum baud rate of 115.2K, if we were to increase the clock rate four-fold we would also increase the baud rate four times to about 460.8K bits per second, roughly 46K bytes per second, so a binary download of all storage memory would take 25 seconds or so. If we double the storage memory to 2 MB we can still dump all that in binary mode in less than a minute. Some serious testing to be done here, how much do we increase the clock rate, do we double it, triple it, quadruple it, and does the increase affect reliability, and if so, how? The 20MHz version of the DIP mentioned above was used in a test unit, operation at 14.6MHz has been verified with no issues.

A minimum of 5 PCBs must be designed no matter what, a Main Board PCB (1), two Memory Board PCBs (2) already done see below, a Power/Charging Board PCB (1) and a Keyboard PCB (1). It is likely that a sixth PCB will be needed to house the analogue circuitry with the ADC and the microcontroller, see the ADC section below.

So the job description is:

1. Double, triple, or quadruple the clock rate from 7.3MHz to 14.6MHz, 21.9MHz, or 29.2MHz
2. Double the storage memory from 1MB to 2 MB
3. Potentially double the EEPROM size from 64K x 8 to 128K x 8
4. Get rid of the lead-acid battery/charging, replace it with NiMH which will instantly more than double capacity
5. Make the move from ±15-bits ADC to ±23-bits ADC and offload the job, min/max, qsort, etc. to a microcontroller, automate calibration
6. Get rid of that ancient keyboard encoder already!
7. Get rid of that DB9 serial connector at unit front, include USB to serial circuitry within unit, outside only needs USB connector